J3/06-323r1 Date: 14 November 2006 To: J3 From: Stan Whitlock / Bill Long Subject: Issue 75, endian ordering Reference: J3/06-007r1, J3/06-231r1, J3/06-293 Discussion of issue 75 (page 494) The second sentence of list item (3) in 16.5.3.2 "Storage sequence" is unnecessary given the more complete explanation of the same issue in Note 16.13 on the following page. The editor recommends deleting the sentence. The editor also requested the example and explanation in Note 16.13 [495:11+] be revised. Edit to 06-007r1: [494:24-25] Delete the sentence "The ordering of these consecutive numeric storage units is processor dependent.". [495:11+] Replace Note 16.13 with For a BITS value, the order of its storage units is processor dependent. For example, BITS X(2) BITS (KIND(X)*2) Y, ZLE, ZBE ... X = TRANSFER (Y, X) ZBE = X(1) // X(2) ZLE = X(2) // X(1) ! ! On some processors, Y==ZLE is true and ! on other processors, Y==ZBE is true